#include "tim.h"

uint16_t timer_period = 0;
uint16_t src_buffer[3] = {0, 0, 0};
static void tim4_gpio_config(void)
{
    gpio_init_type gpio_initstructure;

    /* timer1 output pin Configuration */
    gpio_initstructure.gpio_pins = GPIO_PINS_6;
    gpio_initstructure.gpio_mode = GPIO_MODE_MUX;
    gpio_initstructure.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
    gpio_initstructure.gpio_pull = GPIO_PULL_NONE;
    gpio_initstructure.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
    gpio_init(GPIOB, &gpio_initstructure);
}
static void tim4_dma_config(void)
{
    dma_init_type dma_init_struct;
    /* enable tmr1 overflow dma request */
    tmr_dma_request_enable(TMR4, TMR_OVERFLOW_DMA_REQUEST, TRUE);

    /* dma config for tmr1 overflow dma request */
    /* dma1 channel1 configuration */
    dma_reset(DMA1_CHANNEL1);
    dma_init_struct.buffer_size = 3;
    dma_init_struct.direction = DMA_DIR_MEMORY_TO_PERIPHERAL;
    dma_init_struct.memory_base_addr = (uint32_t)src_buffer;
    dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_HALFWORD;
    dma_init_struct.memory_inc_enable = TRUE;
    dma_init_struct.peripheral_base_addr = (uint32_t)0x40000834; //查手册到TIM4的C1DT的寄存器位置

    dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_HALFWORD;
    dma_init_struct.peripheral_inc_enable = FALSE;
    dma_init_struct.priority = DMA_PRIORITY_MEDIUM;
    dma_init_struct.loop_mode_enable = TRUE;
    dma_init(DMA1_CHANNEL1, &dma_init_struct);

    dma_channel_enable(DMA1_CHANNEL1, TRUE);
}
static void tim4_config(void)
{
    tmr_output_config_type tmr_output_struct;
    /* tmr1 dma transfer example
     tmr1clk = system_core_clock, prescaler = 0, tmr1 counter clock = system_core_clock
     system_core_clock is set to 240 mhz.

     the objective is to configure tmr1 channel 3 to generate complementary pwm
     signal with a frequency equal to 17.57 khz:
        - tmr1_period = (system_core_clock / 17570) - 1
     and a variable duty cycle that is changed by the dma after a specific number of
     update dma request.

     the number of this repetitive requests is defined by the tmr1 repetition counter,
     each 3 update requests, the tmr1 channel 3 duty cycle changes to the next new
     value defined by the src_buffer. */
    /* compute the value to be set in arr regiter to generate signal frequency at 17.57 khz */
    timer_period = (240000000 / 80000) - 1;
    /* compute c1dt value to generate a duty cycle at 50% */
    src_buffer[0] = (uint16_t)(((uint32_t)5 * (timer_period - 1)) / 10);
    /* compute c1dt value to generate a duty cycle at 37.5% */
    src_buffer[1] = (uint16_t)(((uint32_t)375 * (timer_period - 1)) / 1000);
    /* compute c1dt value to generate a duty cycle at 25% */
    src_buffer[2] = (uint16_t)(((uint32_t)25 * (timer_period - 1)) / 100);

    tmr_base_init(TMR4, timer_period, 0);
    tmr_cnt_dir_set(TMR4, TMR_COUNT_UP);

    /* channel 1 configuration in output mode */
    tmr_output_default_para_init(&tmr_output_struct);
    tmr_output_struct.oc_mode = TMR_OUTPUT_CONTROL_PWM_MODE_B;
    tmr_output_struct.oc_output_state = TRUE;
    tmr_output_struct.oc_polarity = TMR_OUTPUT_ACTIVE_LOW;
    tmr_output_struct.oc_idle_state = TRUE;
    tmr_output_struct.occ_output_state = TRUE;
    tmr_output_struct.occ_polarity = TMR_OUTPUT_ACTIVE_LOW;
    tmr_output_struct.occ_idle_state = FALSE;
    /* channel 1 */
    tmr_output_channel_config(TMR4, TMR_SELECT_CHANNEL_1, &tmr_output_struct);
    tmr_channel_value_set(TMR4, TMR_SELECT_CHANNEL_1, src_buffer[0]);

    /* output enable */
    tmr_output_enable(TMR4, TRUE);
    /* enable tmr1 */
    tmr_counter_enable(TMR4, TRUE);
}

void TIM4_Init()
{
    tim4_gpio_config();
    tim4_dma_config();
    tim4_config();
}